Exemplary embodiments of the present invention relate to a semiconductor memory device having a data compression test circuit.
Recently, with the rapid increase in integration of semiconductor memory, a method called a data compression test has been used to test a semiconductor memory device. The data compression test is performed as follows: data having the same logic level are stored in a plurality of cells and then simultaneously outputted to generate a comparison signal.
In the conventional data compression test, when data are stored in a plurality of cells, the data are transmitted through a separate test line coupled between an input buffer and a global line driver. Therefore, during a normal operation, the data are transmitted through a data line between the input buffer and the global line driver, but during a data compression test, the data are transmitted through the separate test line. Accordingly, it is impossible to determine whether a failure occurs in the data line between the input buffer and the global line driver.
Furthermore, in the conventional data compression test, when the comparison signal generated by comparing the data stored in the plurality of cells is outputted, the comparison signal is transmitted through a separate test line coupled between a pipe latch and an output driver. Therefore, during a normal operation, the comparison signal is transmitted through a data line between the pipe latch and the output driver, but during the data compression test, the comparison signal is transmitted through the separate test line. Accordingly, it is impossible to determine whether a failure occurs in the data line between the pipe latch and the output driver.
As such, since the line through which the data and the comparison signal are inputted/outputted during the normal operation and the line through which the data and the comparison signal during the data compression test are not the same, a failure may occur during normal use even though the semiconductor memory device was determined to be normal during the test.